Lecture 9: Packaging & I/O

Part III: Systems Integration — SCE Futures

Table of Contents¶

Learning Objectives¶

By the end of this lecture, you will be able to:

Select appropriate chip carriers and mounting methods for cryogenic applications
Understand wire bonding techniques and materials for cryo environments
Design flip-chip and MCM assemblies for superconducting circuits
Choose appropriate wiring materials balancing thermal load vs signal quality
Implement proper thermal anchoring at each temperature stage
Design filtering and shielding strategies for noise-sensitive measurements
Understand optical I/O options for thermal isolation

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# Setup
import matplotlib.pyplot as plt
import matplotlib.patches as patches
import numpy as np

COLORS = {
    'primary': '#2196F3',
    'secondary': '#FF9800',
    'success': '#4CAF50',
    'danger': '#f44336',
    'dark': '#1a1a2e',
    'light': '#f5f5f5',
    'purple': '#9C27B0',
    'cyan': '#00BCD4',
    'cold': '#00BCD4',
    'warm': '#FF5722',
}

plt.rcParams['figure.facecolor'] = 'white'
plt.rcParams['axes.facecolor'] = 'white'
plt.rcParams['font.size'] = 11

print("Setup complete.")
# Setup
import matplotlib.pyplot as plt
import matplotlib.patches as patches
import numpy as np

COLORS = {
    'primary': '#2196F3',
    'secondary': '#FF9800',
    'success': '#4CAF50',
    'danger': '#f44336',
    'dark': '#1a1a2e',
    'light': '#f5f5f5',
    'purple': '#9C27B0',
    'cyan': '#00BCD4',
    'cold': '#00BCD4',
    'warm': '#FF5722',
}

plt.rcParams['figure.facecolor'] = 'white'
plt.rcParams['axes.facecolor'] = 'white'
plt.rcParams['font.size'] = 11

print("Setup complete.")

Setup complete.

Part 1: Packaging¶

1. Chip Carriers & Mounting¶

Chip Carrier Options¶

Type	Material	Pin Count	Thermal	Best For
Ceramic DIP	Al₂O₃	24-68	Moderate	Prototyping
Ceramic LCC	Al₂O₃	20-84	Moderate	Standard testing
CPGA	Al₂O₃	84-400+	Good	High pin count
Custom PCB	Rogers/Duroid	Any	Varies	RF applications
Cu block	OFHC Cu	Custom	Excellent	High thermal load
Direct mount	N/A	N/A	Best	Maximum cooling

Material Considerations¶

Ceramics (Al₂O₃, AlN):

Good thermal conductivity at cryo (AlN better than Al₂O₃)
CTE mismatch with Si (~7 vs 2.6 ppm/K)
Electrical insulation

Metals (Cu, Au-plated Cu):

Excellent thermal conductivity
Requires insulating layer for electrical isolation
Larger CTE mismatch with Si

PCB (Rogers, Duroid):

Good for RF routing
Lower thermal conductivity
CTE can be tailored

Differential Thermal Contraction¶

Everything shrinks on cooldown, but not equally!

Material	ΔL/L (300K→4K)
Silicon	0.022%
Copper	0.33%
Aluminum	0.41%
Al₂O₃	0.07%
G10/FR4	0.2-0.4%

A 10mm chip on a Cu carrier: Cu shrinks 33μm more than Si → stress!

2. Thermal Contact Methods¶

Getting heat out of the chip requires excellent thermal contact at every interface.

Thermal Interface Materials¶

Material	R_th (typical)	Permanent?	Notes
GE/IMI 7031 varnish	1-10 K/W	Semi	Standard, thin layer
Apiezon N grease	2-20 K/W	No	Crystallizes at cryo
Cry-Con grease	1-10 K/W	No	Stays soft at cryo
Indium foil	0.5-2 K/W	Semi	Conforms to surfaces
Solder	<0.5 K/W	Yes	Best, but permanent
Epoxy (Stycast)	5-50 K/W	Yes	Structural + thermal

Application Tips¶

GE Varnish:

Apply thin layer, let dry partially
Press parts together firmly
Can be removed with solvent

Indium Foil:

Use 0.1-0.5mm thickness
Soft metal conforms to imperfections
Can cold-weld under pressure

Thermal Grease:

Use sparingly (excess increases R_th)
Apiezon N: cheap, but crystallizes
Cry-Con: expensive, better cryo performance

Mounting Hardware¶

Screws: Brass or stainless (not magnetic!)
Spring washers: Maintain pressure through contraction
Clamps: For samples that need to be changed frequently

3. Wire Bonding at Cryogenic Temperatures¶

Wire bonding connects chip pads to package/carrier pads.

Wire Materials¶

Material	Diameter	Resistance	Cryo Performance	Notes
Al (1% Si)	25 μm	Moderate	Good	Standard, reliable
Al (pure)	25-50 μm	Lower	Excellent	Softer, harder to bond
Au	18-25 μm	Low	Good	Expensive

Bonding Techniques¶

Wedge Bonding (Ultrasonic):

Standard for Al wire
Works with Nb pads (with proper metallization)
First bond: pressed and ultrasonically welded
Second bond: similar, then wire broken

Ball Bonding (Thermosonic):

Standard for Au wire
Requires heated stage (~150°C)
Ball formed by spark, pressed to pad

Pad Metallization for Bonding¶

Nb pads alone are difficult to bond to. Common solutions:

Stack	Bondability	Notes
Nb only	Poor	Oxide layer prevents bonding
Nb/Au	Good	Au cap, but watch purple plague
Nb/Al	Good	Al cap, matches Al wire
Nb/Ti/Au	Better	Ti adhesion layer

Cryo-Specific Considerations¶

Thermal cycling stress: Wires flex with each cooldown
- Keep loop height reasonable (not too flat)
- Avoid sharp bends
- Consider redundant bonds for critical signals
Bond strength: Actually improves at cryo (materials harden)
Testing: Pull-test samples before committing to cooldown

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# Visualize: Wire bond geometry
fig, axes = plt.subplots(1, 2, figsize=(12, 5))

# Left: Good wire bond loop
ax = axes[0]
# Chip
chip = patches.Rectangle((0.5, 0.5), 2, 0.3, facecolor=COLORS['primary'], edgecolor='black', linewidth=2)
ax.add_patch(chip)
ax.text(1.5, 0.65, 'Chip', ha='center', va='center', fontsize=10, color='white')

# Package
pkg = patches.Rectangle((3, 0.3), 2, 0.5, facecolor=COLORS['light'], edgecolor='black', linewidth=2)
ax.add_patch(pkg)
ax.text(4, 0.55, 'Package', ha='center', va='center', fontsize=10)

# Bond pads
ax.add_patch(patches.Rectangle((2.2, 0.75), 0.25, 0.1, facecolor='gold', edgecolor='black'))
ax.add_patch(patches.Rectangle((3.1, 0.65), 0.25, 0.15, facecolor='gold', edgecolor='black'))

# Good wire bond - gentle loop
t = np.linspace(0, 1, 50)
x = 2.35 + t * 0.85
y = 0.85 + 0.4 * np.sin(np.pi * t)  # Gentle arc
ax.plot(x, y, 'b-', linewidth=2)
ax.plot([2.35], [0.85], 'ko', markersize=6)  # First bond
ax.plot([3.2], [0.8], 'ko', markersize=6)   # Second bond

# Annotations
ax.annotate('Loop height\n~100-200μm', xy=(2.7, 1.2), xytext=(2.7, 1.6),
            fontsize=9, ha='center', arrowprops=dict(arrowstyle='->', color='black'))
ax.annotate('Bond 1', xy=(2.35, 0.85), xytext=(1.8, 1.0), fontsize=9, ha='center')
ax.annotate('Bond 2', xy=(3.2, 0.8), xytext=(3.7, 1.0), fontsize=9, ha='center')

ax.set_xlim(0, 5.5)
ax.set_ylim(0, 2)
ax.set_aspect('equal')
ax.axis('off')
ax.set_title('Good: Gentle Loop', fontsize=12, fontweight='bold', color=COLORS['success'])

# Right: Bad wire bond examples
ax = axes[1]
# Chip and package
chip = patches.Rectangle((0.5, 0.5), 2, 0.3, facecolor=COLORS['primary'], edgecolor='black', linewidth=2)
ax.add_patch(chip)
pkg = patches.Rectangle((3, 0.3), 2, 0.5, facecolor=COLORS['light'], edgecolor='black', linewidth=2)
ax.add_patch(pkg)
ax.add_patch(patches.Rectangle((2.2, 0.75), 0.25, 0.1, facecolor='gold', edgecolor='black'))
ax.add_patch(patches.Rectangle((3.1, 0.65), 0.25, 0.15, facecolor='gold', edgecolor='black'))

# Bad: Too flat
x_flat = np.linspace(2.35, 3.2, 50)
y_flat = 0.85 + 0.05 * np.sin(np.pi * (x_flat - 2.35) / 0.85)
ax.plot(x_flat, y_flat, 'r-', linewidth=2, label='Too flat (stress)')

# Bad: Sharp bend
ax.plot([2.35, 2.35, 3.2, 3.2], [0.85, 1.4, 1.4, 0.8], 'r--', linewidth=2, label='Sharp bends (fatigue)')

ax.set_xlim(0, 5.5)
ax.set_ylim(0, 2)
ax.set_aspect('equal')
ax.axis('off')
ax.set_title('Bad: Stress Concentrations', fontsize=12, fontweight='bold', color=COLORS['danger'])
ax.legend(loc='upper right', fontsize=9)

plt.tight_layout()
plt.show()

print("Wire bond failures at cryo are usually from:")
print("  1. Thermal cycling stress (too flat = wire can't flex)")
print("  2. Sharp bends (fatigue crack initiation)")
print("  3. Poor initial bond (didn't stick in first place)")
# Visualize: Wire bond geometry
fig, axes = plt.subplots(1, 2, figsize=(12, 5))

# Left: Good wire bond loop
ax = axes[0]
# Chip
chip = patches.Rectangle((0.5, 0.5), 2, 0.3, facecolor=COLORS['primary'], edgecolor='black', linewidth=2)
ax.add_patch(chip)
ax.text(1.5, 0.65, 'Chip', ha='center', va='center', fontsize=10, color='white')

# Package
pkg = patches.Rectangle((3, 0.3), 2, 0.5, facecolor=COLORS['light'], edgecolor='black', linewidth=2)
ax.add_patch(pkg)
ax.text(4, 0.55, 'Package', ha='center', va='center', fontsize=10)

# Bond pads
ax.add_patch(patches.Rectangle((2.2, 0.75), 0.25, 0.1, facecolor='gold', edgecolor='black'))
ax.add_patch(patches.Rectangle((3.1, 0.65), 0.25, 0.15, facecolor='gold', edgecolor='black'))

# Good wire bond - gentle loop
t = np.linspace(0, 1, 50)
x = 2.35 + t * 0.85
y = 0.85 + 0.4 * np.sin(np.pi * t)  # Gentle arc
ax.plot(x, y, 'b-', linewidth=2)
ax.plot([2.35], [0.85], 'ko', markersize=6)  # First bond
ax.plot([3.2], [0.8], 'ko', markersize=6)   # Second bond

# Annotations
ax.annotate('Loop height\n~100-200μm', xy=(2.7, 1.2), xytext=(2.7, 1.6),
            fontsize=9, ha='center', arrowprops=dict(arrowstyle='->', color='black'))
ax.annotate('Bond 1', xy=(2.35, 0.85), xytext=(1.8, 1.0), fontsize=9, ha='center')
ax.annotate('Bond 2', xy=(3.2, 0.8), xytext=(3.7, 1.0), fontsize=9, ha='center')

ax.set_xlim(0, 5.5)
ax.set_ylim(0, 2)
ax.set_aspect('equal')
ax.axis('off')
ax.set_title('Good: Gentle Loop', fontsize=12, fontweight='bold', color=COLORS['success'])

# Right: Bad wire bond examples
ax = axes[1]
# Chip and package
chip = patches.Rectangle((0.5, 0.5), 2, 0.3, facecolor=COLORS['primary'], edgecolor='black', linewidth=2)
ax.add_patch(chip)
pkg = patches.Rectangle((3, 0.3), 2, 0.5, facecolor=COLORS['light'], edgecolor='black', linewidth=2)
ax.add_patch(pkg)
ax.add_patch(patches.Rectangle((2.2, 0.75), 0.25, 0.1, facecolor='gold', edgecolor='black'))
ax.add_patch(patches.Rectangle((3.1, 0.65), 0.25, 0.15, facecolor='gold', edgecolor='black'))

# Bad: Too flat
x_flat = np.linspace(2.35, 3.2, 50)
y_flat = 0.85 + 0.05 * np.sin(np.pi * (x_flat - 2.35) / 0.85)
ax.plot(x_flat, y_flat, 'r-', linewidth=2, label='Too flat (stress)')

# Bad: Sharp bend
ax.plot([2.35, 2.35, 3.2, 3.2], [0.85, 1.4, 1.4, 0.8], 'r--', linewidth=2, label='Sharp bends (fatigue)')

ax.set_xlim(0, 5.5)
ax.set_ylim(0, 2)
ax.set_aspect('equal')
ax.axis('off')
ax.set_title('Bad: Stress Concentrations', fontsize=12, fontweight='bold', color=COLORS['danger'])
ax.legend(loc='upper right', fontsize=9)

plt.tight_layout()
plt.show()

print("Wire bond failures at cryo are usually from:")
print("  1. Thermal cycling stress (too flat = wire can't flex)")
print("  2. Sharp bends (fatigue crack initiation)")
print("  3. Poor initial bond (didn't stick in first place)")

No description has been provided for this image

Wire bond failures at cryo are usually from:
  1. Thermal cycling stress (too flat = wire can't flex)
  2. Sharp bends (fatigue crack initiation)
  3. Poor initial bond (didn't stick in first place)

4. Flip-Chip & MCM Integration¶

Flip-Chip Bonding¶

Chip mounted face-down with solder/metal bumps connecting directly to substrate.

Advantages over wire bonding:

Shorter interconnects → lower inductance
Higher I/O density (area array vs perimeter)
Better thermal path through bumps
More robust mechanically

Bump Materials for Cryo:

Material	Bump Height	Cryo Performance	Notes
Indium	5-20 μm	Excellent	Soft, forgiving, SC below 3.4K
SnPb (legacy)	50-100 μm	Good	Traditional, Pb restrictions
Au stud	20-50 μm	Good	For fine pitch, thermocompression
Cu pillar	30-100 μm	Moderate	High current capacity

Indium bumps are preferred for SCE because:

Indium is superconducting (Tc = 3.4K)
Soft metal accommodates CTE mismatch
Low bonding temperature (room temp possible)

Multi-Chip Modules (MCM)¶

Multiple chips on a common substrate:

flowchart TB
    subgraph mcm[MCM Substrate — Si or Ceramic]
        direction TB
        subgraph chips[" "]
            direction LR
            C1[SCE
Logic]
            C2[SCE
Memory]
            C3[SCE
ADC]
        end
        IC[═══ Superconducting Interconnects ═══]
        C1 --- IC
        C2 --- IC
        C3 --- IC
    end

    style C1 fill:#00BCD4,stroke:#00838F
    style C2 fill:#00BCD4,stroke:#00838F
    style C3 fill:#00BCD4,stroke:#00838F
    style IC fill:#FFD54F,stroke:#F57C00

MCM Benefits:

Mix technologies (Nb logic + NbN detectors, etc.)
Known-good-die assembly (better yield than monolithic)
Shorter die-to-die interconnects than package-to-package

MCM Challenges:

Substrate must support superconducting traces
Alignment tolerance for fine-pitch bumps (<5μm)
Testing/rework after integration

Note on cryo-CMOS: While sometimes proposed for hybrid integration, cryo-CMOS typically dissipates 100s of mW — often negating the efficiency gains of SCE. Generally not recommended unless absolutely necessary.

Part 2: Electrical I/O¶

5. DC & Low-Frequency Wiring¶

For bias currents, control signals, and slow monitoring.

Wire Material Selection¶

Material	Thermal Load	Resistance	Best For
Manganin	Very low	43 μΩ·cm	DC bias, low current
Constantan	Very low	49 μΩ·cm	Thermocouples
Phosphor bronze	Low	10 μΩ·cm	General purpose
NbTi	Near zero (SC)	0 (below Tc)	High-current, best thermal
Copper	High	1.7 μΩ·cm	Short runs at 4K only

Typical Configurations¶

DC bias (e.g., SFQ bias):

Manganin or phosphor bronze twisted pairs
32-36 AWG typical
Filter at room temp and possibly at 4K

Voltage sensing:

4-wire (Kelvin) sensing to eliminate lead resistance
Use same material for all wires in a group

Temperature sensors:

Constantan or phosphor bronze
Shielded twisted pairs for low noise

Thermal Anchoring¶

Critical: Thermalize wires at each temperature stage!

flowchart TB
    RT[Room Temp
Connector] --> A40
    
    subgraph A40[40K Anchor]
        W40[Wrap 5-10 turns
varnish or grease]
    end
    
    A40 --> A4
    
    subgraph A4[4K Anchor]
        W4[Same treatment]
    end
    
    A4 --> DEV[Device]

    style RT fill:#FF5722,color:#fff
    style A40 fill:#FFECB3
    style A4 fill:#00BCD4,color:#fff
    style DEV fill:#4CAF50,color:#fff

Without proper anchoring, heat conducts straight to 4K!

6. RF & High-Speed Signaling¶

SCE circuits can operate at 10+ GHz, requiring careful transmission line design.

Coaxial Cable Options¶

Type	Material	Attn (dB/m @ 10GHz)	Thermal Load	Use
SS semi-rigid	Stainless	3-5	Low	300K↔40K
CuNi semi-rigid	CuNi	2-3	Moderate	300K↔40K
Cu semi-rigid	Copper	0.5-1	High	4K only
NbTi SC coax	Superconducting	~0	Very low	Ultimate
Flexible (SS)	Stainless	4-8	Low	Where flex needed

Thermal Break Strategy¶

Use attenuating (lossy) cables to reduce heat load:

300K ──[SS semi-rigid, 30cm]── 40K ──[SS semi-rigid, 15cm]── 4K ──[Cu, 5cm]── Chip

The SS sections provide thermal isolation; Cu section at 4K preserves signal.

Connector Options¶

Connector	Freq Range	Size	Notes
SMA	DC-18 GHz	Large	Standard, robust
SMP/SMPM	DC-40 GHz	Small	Push-on, space-efficient
2.92mm (K)	DC-40 GHz	Medium	High performance
1.85mm (V)	DC-67 GHz	Small	Very high frequency

Cryo considerations:

Connectors may need re-torque after thermal cycling
SMP push-on connectors are convenient for sample changes
Hermetic feedthroughs required at vacuum boundary

7. Filtering & Amplification¶

Why Filter?¶

Noise from room temperature electronics can swamp sensitive cryo measurements:

Thermal noise: ~4 kT bandwidth
EMI/RFI pickup
Digital switching noise

Filter Types¶

Type	Cutoff	Attenuation	Location	Notes
RC (lumped)	1-100 MHz	20-40 dB	Any	Simple, cheap
LC (lumped)	Tunable	40-60 dB	Any	Sharper rolloff
Powder (metal powder)	1-10 GHz	60-100 dB	Cryo	Excellent HF
Eccosorb	>1 GHz	40-60 dB	Cryo	Absorptive
Copper powder	100 MHz-10 GHz	80-120 dB	Cryo	Best attenuation

Filter Placement¶

flowchart TB
    RT[Room Temp Electronics] --> F1
    
    subgraph F1[RT Filter]
        RF1[Blocks EMI from
entering cryostat]
    end
    
    F1 --> VF[─── Vacuum Feedthrough ───]
    VF --> A40[40K Anchor]
    A40 --> F2
    
    subgraph F2[4K Filter]
        RF2[Blocks thermal
radiation in wires]
    end
    
    F2 --> DEV[Device]

    style RT fill:#FF5722,color:#fff
    style F1 fill:#FFF9C4
    style F2 fill:#BBDEFB
    style DEV fill:#4CAF50,color:#fff

Cryogenic Amplifiers¶

For weak signals, amplify at 4K before thermal noise accumulates:

Type	Noise Temp	Gain	Power	Notes
HEMT	2-10 K	25-40 dB	5-15 mW	Workhorse, commercial
SiGe HBT	10-30 K	20-30 dB	1-5 mW	Lower power
JPA	~quantum limit	20 dB	μW	Narrowband, complex
TWPA	~quantum limit	20 dB	μW	Broadband, cutting-edge

HEMT amplifiers (Low Noise Factory, Cosmic Microwave) are the standard choice.

8. Grounding & Shielding¶

Ground Loop Prevention¶

Ground loops cause low-frequency noise and can completely mask small signals.

Star Ground Topology: All grounds connect at ONE point (typically cryostat chassis), no loops.

Coax Shield Grounding¶

Single-end grounding: Ground the coax shield at the warm end (feedthrough) only. Do NOT connect the shield to ground at the cold end.

Why? A shield grounded at both ends creates a loop between 300K and 4K. Temperature-dependent thermoelectric voltages and conducted noise will flow through this loop.

What about getting ground to the chip?

The coax center conductor carries the signal to the PCB. The chip's ground reference comes from:

PCB ground plane — a continuous copper layer on the interposer/PCB
Single chassis connection — PCB ground connects to cryostat chassis at ONE point
Multiple wirebonds — chip ground pads connect to PCB ground plane via MANY wirebonds

This is not a contradiction:

Coax shields: single-end ground (prevents warm-cold loops)
Chip wirebonds: multiple ground bonds (low inductance for RF return)
PCB to chassis: single point (star ground topology)

RF ground return: For high-frequency signals, you need low-inductance ground return paths. Use multiple ground wirebonds distributed around the signal bonds. These all connect to the same ground plane — this is NOT a ground loop, it's a low-inductance return path.

Two-Domain Ground Isolation¶

For µV-level measurements (AQFP readout), even star grounding may be insufficient. The cryostat body couples to building ground through the compressor/cold head chain.

Two-domain architecture separates:

Domain 1 (Earth): Building mains → compressor → cold head → cryostat body
Domain 2 (Isolated): Isolation transformer → readout electronics → dedicated ground wires → 4K PCB

The domains are electrically isolated by:

Alumina disk at 4K (thermally conductive, electrically insulating) between cold finger and measurement PCB
Isolation transformer feeding all readout electronics

This keeps compressor motor noise and 50/60 Hz building ground noise in Domain 1, while measurements reference the quiet Domain 2 ground.

See Lecture 11 (Testing) and the ground_isolation_memo technical note for detailed implementation.

Common Grounding Mistakes¶

Mistake	Symptom	Fix
Shield grounded both ends	50/60 Hz noise, ground loop	Ground at warm end ONLY
Single ground wirebond to chip	Poor RF return, ringing	Multiple ground bonds
PCB ground at multiple chassis points	Ground loop	Single star point
Digital and analog share ground	Switching noise	Separate grounds, join at star
No chassis ground	EMI pickup	Ground cryostat chassis

Shielding¶

Cable shielding:

Twisted pairs: Reject magnetic pickup
Braided shield: Good flexibility, moderate shielding
Solid shield (semi-rigid): Best shielding, no flexibility

Magnetic shielding at 4K:

Finemet: High permeability, no annealing needed
Cryoperm: Similar performance
Lead (Pb): Superconducting shield below 7.2K, perfect diamagnetic shielding

RF shielding:

Copper or aluminum enclosures
All seams must make good contact
Filtered feedthroughs for DC lines

Part 3: Advanced I/O¶

9. Optical I/O¶

Optical fiber offers unique advantages for cryogenic I/O:

Advantages¶

Zero electrical heat conduction: Only photon energy
Extremely high bandwidth: 100+ Gbps possible
Complete galvanic isolation: No ground loops
EMI immunity: No pickup in fiber

Fiber Types¶

Type	Core	Bandwidth	Cryo Behavior
Single-mode (SMF-28)	9 μm	Highest	Works well
Multi-mode (OM4)	50 μm	Lower	Works well
Polarization-maintaining	9 μm	High	Birefringence shifts

Cryo-Optical Considerations¶

Fiber contraction: ~0.1% from 300K to 4K
- Leave slack in fiber routing
- Avoid tight bends (becomes brittle)
- Minimum bend radius ~10mm at cryo
Connectors:
- FC/PC, FC/APC work at cryo
- May need realignment after first cooldown
- Use vacuum-compatible feedthroughs
Detectors at 4K:
- InGaAs photodiodes: work but reduced responsivity
- Ge photodiodes: good cryo performance
- SNSPDs: superconducting, for single photons

Applications¶

Clock distribution: Low-jitter optical clock to 4K
High-bandwidth data input: Streaming data into cryogenic systems with minimal heat load

10. Flex PCB / Kapton Wiring¶

Flexible printed circuits offer advantages for cryogenic wiring:

Why Flex/Kapton?¶

Consistent geometry: Controlled impedance, repeatable
Low mass: Less thermal anchoring needed
High density: Many traces in small space
Flexible: Can bend around corners
Kapton survives cryo: -269°C to +400°C range

Design Considerations¶

Parameter	Typical Value	Notes
Trace width	75-150 μm	Finer for high density
Trace spacing	75-150 μm	Limited by manufacturing
Copper thickness	9-35 μm	Thinner = less heat load
Kapton thickness	25-50 μm	Standard polyimide
Impedance	50Ω typical	For RF traces

Thermal Performance¶

Heat load per flex cable: $$Q = n_{traces} \cdot \frac{A_{trace}}{L} \int k_{Cu}(T) \, dT$$

Example: 20-trace flex, 9μm Cu, 50mm long, 300K→4K:

~50 mW total (compare to 20× individual wires: ~200 mW)

Flex Cable Routing¶

flowchart TB
    RT[Room Temp Connector
ZIF / board-to-board]
    
    RT --> F1
    subgraph F1[Flex Cable]
        S1[Serpentine
for length]
    end
    
    F1 --> T40[40K Thermalization]
    T40 --> F2
    
    subgraph F2[Flex Cable]
        S2[Continues
to 4K]
    end
    
    F2 --> DUT[4K Connection
to DUT]

    style RT fill:#FF5722,color:#fff
    style T40 fill:#FFECB3
    style DUT fill:#00BCD4,color:#fff
    style F1 fill:#FFF9C4
    style F2 fill:#FFF9C4

11. Practical Wiring Guidelines¶

Design Rules Summary¶

Minimize wire count: Each wire is a thermal leak
Use appropriate materials: Balance thermal vs signal quality
Thermalize at every stage: 5-10 wraps with varnish/grease, or thermal clamps
Route carefully: Separate digital from analog
Document everything: Label wires, keep wiring diagrams

Material Selection Quick Reference¶

Application	Material	AWG	Notes
DC bias (<10 mA)	Manganin	36	Lowest thermal load
DC bias (>10 mA)	NbTi	32-36	Zero resistance below Tc
Digital signals	Phosphor bronze	32-36	Good balance
RF (300K→40K)	SS coax	-	Thermal isolation
RF (40K→4K)	SS coax	-	Continued isolation
RF (at 4K)	Cu coax	-	Low loss
Thermometry	Phosphor bronze	32-36	Twisted pair, shielded

Checklist Before Cooldown¶

All wires thermally anchored at 40K and 4K
Continuity verified at room temperature
No shorts between channels
Shields connected (at one end only)
Connectors tight and labeled
Wiring diagram documented
Spare wires for contingency

In [3]:

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# Visualize: Complete wiring scheme for SCE test system
fig, ax = plt.subplots(figsize=(14, 10))

# Temperature stages
stages = [
    (8.5, 12, 1, '300 K', COLORS['warm']),
    (6, 10, 1.2, '40 K', '#FFECB3'),
    (3, 8, 1.5, '4 K', COLORS['cold']),
]

for y, w, h, label, color in stages:
    rect = patches.FancyBboxPatch(((14-w)/2, y), w, h, boxstyle="round,pad=0.05",
                                   facecolor=color, alpha=0.4, edgecolor='black', linewidth=2)
    ax.add_patch(rect)
    ax.text(7, y + h/2, label, ha='center', va='center', fontsize=11, fontweight='bold')

# DUT
dut = patches.FancyBboxPatch((5.5, 3.3), 3, 0.8, boxstyle="round,pad=0.02",
                              facecolor=COLORS['secondary'], edgecolor='black', linewidth=2)
ax.add_patch(dut)
ax.text(7, 3.7, 'SCE DUT', ha='center', va='center', fontsize=11, fontweight='bold')

# Wiring paths
wire_configs = [
    (2, 'DC Bias\n(Manganin)', COLORS['success'], [9.5, 7.2, 4.5, 3.7]),
    (4, 'Digital I/O\n(PhBr TP)', COLORS['primary'], [9.5, 7.2, 4.5, 3.7]),
    (6, 'Clock\n(SS coax)', 'gray', [9.5, 7.2, 4.5, 3.7]),
    (8, 'RF Out\n(SS→Cu)', COLORS['purple'], [9.5, 7.2, 4.5, 3.7]),
    (10, 'Optical\n(SMF)', COLORS['cyan'], [9.5, 7.2, 4.5, 3.7]),
]

for x, label, color, ys in wire_configs:
    # Draw wire path
    ax.plot([x, x], [ys[0], ys[1]], color=color, linewidth=2.5)
    ax.plot([x, x], [ys[1], ys[2]], color=color, linewidth=2.5)
    ax.plot([x, x], [ys[2], ys[3]], color=color, linewidth=2.5)
    
    # Thermal anchors at 40K and 4K
    for y_anchor in [7.2, 4.5]:
        circle = plt.Circle((x, y_anchor), 0.15, facecolor='gold', edgecolor='black', linewidth=1, zorder=5)
        ax.add_patch(circle)
    
    # Labels
    ax.text(x, 10, label, ha='center', va='bottom', fontsize=9)

# HEMT amplifier
hemt = patches.Rectangle((7.7, 4.2), 0.6, 0.4, facecolor=COLORS['purple'], edgecolor='black', linewidth=1.5)
ax.add_patch(hemt)
ax.text(8, 4.4, 'HEMT', ha='center', va='center', fontsize=7, color='white')

# Filter symbols
ax.text(2, 9.2, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))
ax.text(4, 9.2, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))
ax.text(2, 4.8, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))

# Legend
ax.text(12.5, 8, 'Legend:', fontsize=10, fontweight='bold')
ax.text(12.5, 7.5, '● Thermal anchor', fontsize=9)
ax.text(12.5, 7.0, 'F  Filter', fontsize=9)
ax.text(12.5, 6.5, 'TP = Twisted pair', fontsize=9)

ax.set_xlim(0, 14)
ax.set_ylim(2.5, 10.5)
ax.axis('off')
ax.set_title('Complete SCE Test System Wiring Scheme', fontsize=14, fontweight='bold')

plt.tight_layout()
plt.show()
# Visualize: Complete wiring scheme for SCE test system
fig, ax = plt.subplots(figsize=(14, 10))

# Temperature stages
stages = [
    (8.5, 12, 1, '300 K', COLORS['warm']),
    (6, 10, 1.2, '40 K', '#FFECB3'),
    (3, 8, 1.5, '4 K', COLORS['cold']),
]

for y, w, h, label, color in stages:
    rect = patches.FancyBboxPatch(((14-w)/2, y), w, h, boxstyle="round,pad=0.05",
                                   facecolor=color, alpha=0.4, edgecolor='black', linewidth=2)
    ax.add_patch(rect)
    ax.text(7, y + h/2, label, ha='center', va='center', fontsize=11, fontweight='bold')

# DUT
dut = patches.FancyBboxPatch((5.5, 3.3), 3, 0.8, boxstyle="round,pad=0.02",
                              facecolor=COLORS['secondary'], edgecolor='black', linewidth=2)
ax.add_patch(dut)
ax.text(7, 3.7, 'SCE DUT', ha='center', va='center', fontsize=11, fontweight='bold')

# Wiring paths
wire_configs = [
    (2, 'DC Bias\n(Manganin)', COLORS['success'], [9.5, 7.2, 4.5, 3.7]),
    (4, 'Digital I/O\n(PhBr TP)', COLORS['primary'], [9.5, 7.2, 4.5, 3.7]),
    (6, 'Clock\n(SS coax)', 'gray', [9.5, 7.2, 4.5, 3.7]),
    (8, 'RF Out\n(SS→Cu)', COLORS['purple'], [9.5, 7.2, 4.5, 3.7]),
    (10, 'Optical\n(SMF)', COLORS['cyan'], [9.5, 7.2, 4.5, 3.7]),
]

for x, label, color, ys in wire_configs:
    # Draw wire path
    ax.plot([x, x], [ys[0], ys[1]], color=color, linewidth=2.5)
    ax.plot([x, x], [ys[1], ys[2]], color=color, linewidth=2.5)
    ax.plot([x, x], [ys[2], ys[3]], color=color, linewidth=2.5)
    
    # Thermal anchors at 40K and 4K
    for y_anchor in [7.2, 4.5]:
        circle = plt.Circle((x, y_anchor), 0.15, facecolor='gold', edgecolor='black', linewidth=1, zorder=5)
        ax.add_patch(circle)
    
    # Labels
    ax.text(x, 10, label, ha='center', va='bottom', fontsize=9)

# HEMT amplifier
hemt = patches.Rectangle((7.7, 4.2), 0.6, 0.4, facecolor=COLORS['purple'], edgecolor='black', linewidth=1.5)
ax.add_patch(hemt)
ax.text(8, 4.4, 'HEMT', ha='center', va='center', fontsize=7, color='white')

# Filter symbols
ax.text(2, 9.2, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))
ax.text(4, 9.2, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))
ax.text(2, 4.8, 'F', fontsize=10, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black'))

# Legend
ax.text(12.5, 8, 'Legend:', fontsize=10, fontweight='bold')
ax.text(12.5, 7.5, '● Thermal anchor', fontsize=9)
ax.text(12.5, 7.0, 'F  Filter', fontsize=9)
ax.text(12.5, 6.5, 'TP = Twisted pair', fontsize=9)

ax.set_xlim(0, 14)
ax.set_ylim(2.5, 10.5)
ax.axis('off')
ax.set_title('Complete SCE Test System Wiring Scheme', fontsize=14, fontweight='bold')

plt.tight_layout()
plt.show()

12. Summary¶

Key Concepts¶

Packaging:

CTE mismatch is the enemy: Si shrinks less than Cu/ceramics
Thermal contact: varnish, indium, grease — minimize interface resistance
Wire bonding works at cryo with Al wire and proper loop geometry
Flip-chip with indium bumps is ideal for high-density SCE

DC Wiring:

Manganin for lowest thermal load (DC bias)
NbTi for zero-resistance high-current lines
Phosphor bronze for general purpose
Thermalize at EVERY temperature stage

RF Wiring:

SS coax for thermal isolation (300K↔40K↔4K)
Cu coax only at 4K (low loss)
HEMT amplifiers at 4K for sensitive readout

Grounding & Shielding:

Star ground topology, one ground point
Shield grounded at ONE end only
Finemet or lead for magnetic shielding at 4K

Common Mistakes to Avoid¶

Cu wire from 300K to 4K (massive heat load)
No thermal anchoring (heat goes straight to 4K)
Ground loops (50/60 Hz noise)
Shields grounded both ends (ground loop)
Wires too short (strain on cooldown)

Quick Reference¶

Application	Material	Key Specs
DC bias	Manganin	36 AWG, twisted pair
High current	NbTi	SC below 9K
RF thermal break	SS coax	3-5 dB/m @ 10 GHz
RF at 4K	Cu coax	<1 dB/m @ 10 GHz
Flex wiring	Kapton/Cu	9-18 μm Cu
Optical	SMF-28	Works at cryo